A 1.6W, 40MHz power amplifier

Considering class AB and class B bias configuration in power amplifier, for class AB bias design, it provides a better power gain, so it require less driving power, but the drawback is the power transistor pass a quit heavy idle current, for this reason, the overall power efficiency is low. When the output power required is approaching the thermal limit of transistor, the low efficiency cause a problem , pushing the transistor got overheat and burn up before it can generate a good output power.

In this attempt of 40MHz power amplifier, the objective is to squeeze as much power as possible from a BLT50 transistor, the class B bias configuration is selected because of the better efficiency.

Using power supply of 10V, 647mA of current, an output power of 1.6W is achieved.

Two stages is required because the second stage class B amplifier required a pretty large drive power ~20dBm (100mW). L1 is 0.8mm wire with 7mm diameter, 7T. L2 is 0.8mm wire with 7mm diameter, 3T.

Spectrum analyzer shows 26dBm,incorporate with two -3db attenuator, the output power is 32dBm(1.6W). the second harmonic having a level of ~15 db below the fundamental.

The two-stage power amplifier consumes 0.647A of current, at 10V.

Input drive power required 5dBm.

Having adequate heat sink is important because the heavy power dissipation can burn the transistor up.

The waveform for power stage collector. Actual voltage is 4 times larger than the probed voltage, due to the resistor voltage divider.

The waveform for output matching circuit. The circuit consist of L2 and C1 L-section. Actual voltage is 4 times larger than the probed voltage, due to the resistor voltage divider.

The output voltage is measured 28V p-p which is larger than twice of the DC supply voltage 10V, because of the output impedance matching circuit.

RF Probing issue

When probing around a 500mW 40MHz power amplifier. There is an observation of leaked RF signal on oscilloscope probe, even it is grounded like the picture above.

the leak pickup may caused by the probe ground tail inductance.

And the leaked signal is quite strong, it is suspected that the antenna radiate the carrier around the board. 

This leaked RF pickup may contribute to the unexpected waveform during measurement. This probe is on the collector of transistor.

which is not expected to having voltage dip below 0V

The measurement method needed to be revised.

RF active probe, or differential probe would they help?

Reflow soldering exploration

Soldering using hand is slow and not easy in quality control, so try reflow soldering method, a solder paste in syringe package is bought and, it contains Sn63/Pb37.

Solder paste is usually apply through solder paste stencil and we don't have a stencil today, we apply it by hand, it takes a steady hand.

next step is placing components on the pads, requires steady hand and intense focus. the pads is bit sticky because of the solder paste, i can't see clearly if the SOIC package IC AD607 is correctly placed, i hope it would goes to the right alignment during reflow.

and insert the board into reflow oven. heat it up using the default temperature profile. it takes about 10 mins, with some bad smell.

after reflow, most of the component is properly soldered, we noticed there are two pins on AD607 is falsely joined together, because of too much solder paste, and some legs of resistor array is not soldered, because the solder paste is not enough, and the lower left side clock IC is drifted away from the pad totally, because the pads are too apart and it not suit for reflow soldering.

The reflow soldering process looks good and it saved a huge amount of manual soldering time, it can be improve in the way that some pads needs to revise in shape to suit for reflow soldering.

a feedforward bpsk demodulation algorithm

SDR receiver system development board

a completed software defined radio receiver system development board, covered frequency range up to 500MHz. going to submit to PCB factory. This design utilized programmable MEMS oscillator as local oscillator.

MIXER and IF amplifier chain: AD607 IF sub-system

ADC: AD9201 dual channel 10-bits ADC

Signal processing: PIC32MX MIPS based microcontroller

USB connectivity: FT245R USB-parallel FIFO

SI501 32kHz to 100MHz Programmable oscillator

Silicon labs SI501 one-time-programmable CMEMS Oscillator

We use crystals oscillator to generate local oscillator, however crystal oscillator comes with fixed frequency and we can only pick the standard frequencies listed by manufacturer, sometimes we needs a particular frequency which is not available in the market. Recently there are some programmable oscillator IC on the market, and these IC using on-chip MEMS resonator as source and PLL circuitry to convert the base frequency to the target frequency, in the range of 32kHz to 100MHz. 

The programmer, comes with a windows GUI, through USB.

I hope I can use these oscillator to replace some of the crystal oscillator in the projects

detect a signal in a noisy enviroment

to detect a signal in a noisy enviroment, setting a received power level threshold doesnt always work, because noise power often varies, for example in a quiet enviroment, the noise power is -100dbm and we think its ok to set a threshold at -90 dbm and anything above -90dbm is a signal, it works until we moved to an enviroment that is abit more noisy, say -80dbm noise and -70 dbm signal, then we would falsely report that there's always having a signal present.

what does really matter is the signal to noise ratio.

we have to normalize the receiver gain such that the output of receiver amplifier chain is always closed to saturated, in the above example we should normalize the received signal to 0dbm so the noise become -10 dbm. And the demodulator should always try its best to perform demodulation, once the  received signal to noise ratio is above a certain level, the demodulator would giving correct output data, by verifing the checksum of demodulated data, we can report with confident that a signal is presented.

Mini-circuit ADE-1 mixer DC modulation measurement

Input DC voltage is applied to IF port, RF input:40MHz, 5dBm

Voltage mV	Current mA	Attenuation db
600	130	5.1
550	105	5.3
500	79	5.6
450	54	6
400	31	6.4
350	14	7.1
300	6	8.3
250	4	10.3
200	3	13.1
150	2	15.2
130	1	19
100	1	23
80	1	28
60	0.5	37

Mini-circuit ADE-1 mixer S11 Reflection coefficient measurement

The mini-circuit ADE-1 mixer is a diode-ring type passive mixer. As a +7dBm mixer work best at +7dBm of local oscillator input, or at least +4dBm to make it start working. It sounds like a quite huge power, so may be impedance matching is needed to optimize the efficiency of driving this mixer.  

How to do impedance matching? ok, may be we need to know the impedance of this particular component. As not very obviously showing in the picture, the IF and RF port of the mixer is connected to 50 ohm resistor for proper termination.The LO port is connected to the network analyzer for reflection coefficient measurement. Through a 1nF (-16j ohm@10MHz to -1.6j ohm@100MHz) capacitor in series.

The network analyzer is set to 10MHz to 100MHz, in -10dBm low power level, it have a quite high impedance(313ohm@10MHz) and a bit of capacitive (-22j ohm@10MHz).

In -5dBm power level, it's impedance is lowered.

In 0dBm, it's impedance is quite close to 50ohm

In +4dBm, even lower.

In +7dBm, even lower

In +10dBm, Well, it's quite hard to drive because impedance is quite low.

HF band ADF4002 PLL Test

The 36.5-50MHz ADF4002 PLL-VCO circuitry is completed.

The VCO having a tunning range of 36.5MHz ~ 50MHz from 0V to 5V, that translate to sensitivity of  2.7MHz/V. 

The sensitivity of VCO is used to feed into ADIsimPLL tool, generate a second order loop filter of  1KHz bandwidth, 100kHz phase detector frequency and charge pump current 5mA.

The PLL is programmed to lock to 40.0MHz, some noise is observed.

Compare with the output spectrum of Agilent E4432 Signal generator, which is very nice and clean.

Is the PLL phase noise performance good enough? The noise is from VCO or loop filter? 

The bandwidth limit of a small dipole antenna matching circuit

If we model the antenna as an RC circuits, no matter how sophisticated the matching circuits is, the best bandwidth we can get is given by the formula :

T is gain and R is the real component of antenna impedance and C is the equivalence input capacitance of antenna. This equation suggest that the larger the real component of the antenna impedance, the better bandwidth we can get. And the Larger capacitance, the better bandwidth we can get.

REFERENCE

V. Iyer , S. N. Makarov , D. D. Harty , F. Nekoogar and R. Ludwig  "A lumped circuit for wideband impedancematching of a non-resonant, short dipole or monopole antenna",  IEEE Trans. AntennasPropag.,  vol. 58,  no. 1,  pp.18 -26 2010 

Short dipole antenna impedance model (Python code)

from math import log
from numpy import pi, tan
from numpy.polynomial.polynomial import polyval


# Short dipole antenna impedance model

f = 27e6             # frequency
La = 1.4             # total dipole length
Dia = 0.001          # diameter of the conductor

wavelen = 3e8/f
k = 2*pi/wavelen     # wave number
z = k*La/2;
R = polyval(z, [-0.4787, 7.3246, 0.3963, 15.6131])
X = polyval(z, [-0.4456, 17.00826, -8.6793, 9.6031])
IM = 120*(log(La/Dia)-1.0) * 1.0/tan(z) - X

print  'Real:', R, ' Imag:', IM

Matching network design by random guess

Read an article named "A Lumped Circuit for Wideband Impedance Matching of a Non-Resonant, Short Dipole or Monopole Antenna", this article suggested a 5-elements wideband matching network with some both low pass and high pass sections and so it say it's a wideband matching network.

Then I trying to apply this circuit to 27.0MHz band, and a python code is made to randomly guess the 5 component values and evaluate the performance by calculating the reflection coefficient at 5 frequency point around 27.0MHz. After millions cycles of guess, this is the best result I can get.

L1 : 4.04e-06

L2 : 2.918e-07

C1 : 2.247e-11

L3 : 7.131e-07

C2 : 2.312e-11

These value is put into Agilent ADS to verify. With reflection magnitude plot and smith chart plot.

The green plot is the baseline reference matching result using simple 1-element matching and the blue plot is from the 5-element. The 5-element matching network appeared having a wider bandwidth compare to that of 1-element network. 

Promising.

Impedance matching bandwidth simulation test

Cascaded L-section matching network between 50 ohm source and 25 ohm load, @ 27.0MHz, using 1 L-section, 2 L-sections and 3 L-sections, all of the three configuration would matching perfectly at exactly one frequency point, that is 27.0MHz. However in many case we want good matching on a wider bandwidth. The question is, can a 3-section matching network works better than a single L-section?

Well, from the frequency response plot and reflection plot, we can see the bandwidth of 3-section network is not significantly wider than that of the single section.

Some other matching network topology need to be investigate to achieve the goal of broadband matching.

27MHz monopole antenna impedance measurement

500mm long AWG28 wire antenna, in serial with variable inductor, for matching.

Return loss in Smith chart plot, from 10MHz to 40MHz, at 28MHz, only real component remain.

Return loss in log magnitude plot, dip around 28MHz, quite narrow band, look like not very good.

Return loss phase plot